What is the difference between latency and throughput?

I've been working in an Electrical and Electronic Engineering department for more than three years now, but I admit that it's only quite recently that I find myself properly understanding the difference between latency and throughput. These are terms that are used all the time when talking about an electronic circuit. The distinction between them…

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Greatest Hits of FCCM 2018

I had a great time in Boulder, Colorado at the FCCM 2018 conference last week. Here are a few of the papers that I found particularly interesting: Siddhartha and Kapre's paper, Hoplite-Q: Priority-Aware Routing in FPGA Overlay NoCs, was about how to build a "network-on-chip"; that is, a miniature network that allows the various components of…

Concurrency-aware scheduling for high-level synthesis

What follows is a summary of the main contributions of a paper by Nadesh Ramanathan, George Constantinides, and myself that will be presented at the FCCM 2018 conference. If you want to compute something, you have two broad options: do it in software, or do it in hardware. A custom piece of hardware can give you…

What do you get if you cross Weak Memory with Transactional Memory?

What follows is a summary of the main contributions of a paper I wrote with Nathan Chong and Tyler Sorensen for the PLDI 2018 conference. This project studies two features of a modern computer, one called out-of-order execution and one called transactional memory. Out-of-order execution is where a computer chooses, for performance reasons, to perform its instructions in an order…

Who has the most POPL and PLDI papers?

DBLP is an online database of academic publications in computer science and related fields. Handily, it provides a Java API for accessing the data programmatically. In this blog post, I share a few fun facts I discovered while using this API to explore the data that DBLP holds about two of the main conferences on…

So, who has the most FPGA, FCCM, FPL, and FPT papers?

DBLP is an online database of academic publications in computer science and related fields. Handily, it provides a Java API for accessing the data programmatically. In this blog post, I share a few fun facts I discovered while using this API to explore the data that DBLP holds about four conferences on FPGA technology; namely,…

Ribbon Diagrams for Weak Memory

In their POPL'17 paper, Shaked Flur, Susmit Sarkar, Christopher Pulte, Kyndylan Nienhuis, Luc Maranget, Kathy Gray, Ali Sezgin, Mark Batty, and Peter Sewell describe a semantics of weakly-consistent memory that copes (for the first time) with mixed-size memory accesses. In this blog post, I describe how their semantics can be explained rather nicely with some graphical…

Translating lock-free, relaxed concurrency from software into hardware

What follows is a summary of the main contributions of a paper I wrote with Nadesh Ramanathan, Shane Fleming, and George Constantinides for the FPGA 2017 conference. Languages like C and C++ allow programmers to write concurrent programs. These are programs whose instructions are partitioned into multiple threads, all of which can be run at the same time.…

Memory Consistency Models, and how to compare them automatically

My POPL 2017 paper with Mark Batty, Tyler Sorensen, and George Constantinides is all about memory consistency models, and how we can use an automatic constraint solver to compare them. In this blog post, I will discuss: What are memory consistency models, and why do we want to compare them? Why is comparing memory consistency…

cppreference.com gets acquire/release instructions wrong

It is quite well-known that the memory operations and fences provided by the C/C++11 languages are pretty complicated and confusing. For instance, my OOPSLA 2015 paper (joint with Batty, Beckmann, and Donaldson) explains that a proposed implementation of these instructions for next-generation AMD graphics cards is faulty because the designers misunderstood how they worked. And…